Electric Frequently Asked Questions

As bugs are discovered in the current release of Electric, they are posted here.

Yes. Electric is 64-bit clean and has been successfully run on many 64-bit computers.

When reading CIF or GDS files, Electric needs to know which layers in the files correspond to layers in Electric. Electric has a separate set of layer maps for every technology. Therefore, you must make sure (1) that the desired technology is the current one and (2) that the layers in that technology match the layers in your CIF / GDS file.

Since Electric drawings consist of connected parts, and since CIF and GDS have no connectivity in them, this means that imported CIF and GDS does not contain the necessary information for full Electric design. You can still view the files, and you can still include them in mask output. However, many Electric tools (such as network analysis and DRC) will not properly understand the layout. Use the Node Extractor to convert the artwork to full Electric components.

No. The VHDL compiler only accepts structural VHDL (just the interconnect of components). This compiler is old, and it simply doesn't support modern VHDL constructs.

Each technology in Electric supports a specific set of design parameters. None of the CMOS layout technologies have 4-terminal transistors. However, the schematic technology does have 4-terminal transistors.

The library that is distributed with the silicon compiler is not actually valid for chipmaking. The reason for this is that the library is derived from an older one which was much larger in scale. By scaling that library down to submicron sizes, it was able to be used by the silicon compiler. However, no effort has been made to ensure that the scaling was correct, or that any of the cells are still valid. Thus, the library is purely for "illustration purposes."

If you wish to construct a library for use with the silicon compiler, simply create the cells that exist in the current library ("and2", "and3", "or2", "inverter", etc.) Be sure that the cells follow the form used in the library (i.e. horizontal power and ground rails along the top and bottom, all other interconnect done vertically, same port names for power, ground, inputs, and outputs). You will then have to set the various parameters in the "Silicon Compiler" preferences. If you have a library, and wish to make it available for other users, contact Static Free Software for help with the intergration.

Static Free Software is an Artisan Components EDANet partner. As a result, users can join the Artisan program and then get standard cell libraries for use in layout and in the Silicon Compiler.

Everything else that we have is given away for free. All of the "technology files" are built-in. Additional ones can be created, and as they do, they will become part of the distribution.

An example chip, with over 1,000,000 transistors, is available for download here. This chip measures on-chip and inter-chip capacitance structures. It was designed by the Asynchronous Design Group of Sun Microsystems.

Static Free Software is an Artisan Components EDANet partner. As a result, users can join the Artisan program and then download standard cell libraries for use in layout and in the Silicon Compiler.

Anyone who has created circuitry that they wish to share with the Electric community should contact Static Free Software. Your designs could be the cornerstone of other people's work.