Chapter 9: Tools
9-9: Logical Effort

The Logical Effort tool examines a digital schematic and determines the optimal transistor size to use in order to get maximum speed. The tool is based on the book Logical Effort, by Ivan Sutherland, Bob Sproull, and David Harris (Morgan Kaufmann, San Francisco, 1999). It is highly recommended that the user be familiar with the concepts of this book before using the Logical Effort Tool.

To control Logical Effort, use the Logical Effort Preferences (in menu File / Preferences..., "Tools" section, "Logical Effort" tab). This lets you control a number of settings for Logical Effort analysis.
Figure 9.14

Logical Effort Gates

A design that is intended to be analyzed with Logical Effort must be composed of special Logical Effort gates. A Logical Effort gate is simply a schematic or layout cell that conforms to the following specifications:

Figure 9.25

On the input and output exports of the cell, we can define an attribute named "le" (use the Add LE Attribute to Selected Export command in menu Tools / Logical Effort to add this attribute). The value of this attribute is the logical effort of that port. For example, a NAND gate typically has a logical effort on each input of 4/3, and an output logical effort of 2. An inverter is defined to have an input logical effort of 1, and an output logical effort of 1.

The size assigned to the logical effort gate is retrieved via the "LE.getdrive()" call. This value can then be used to size transistors within the gate. The size retrieved is scaled with respect to a minimum sized inverter (as are all other logical effort parameters). So a size of "1" denotes a minimum sized inverter.

While these attributes are defined on the layout or schematic cell definition, they must also be present on the instantiated icon or instance of that definition. By default this will be so.

Finally, there must be at least one load that is driven by the gates in order for them to be sized. A load is either a transistor or a capacitor. Gates that do not drive loads, or that do not drive gates that drive loads, will not be assigned sizes.

Logical Effort Libraries

Electric comes with a set of libraries that are specially designed for Logical Effort. Use the Load Logical Effort Libraries (Purple, Red, and Orange) command (in menu Tools / Logical Effort) to read these libraries.

Advanced Features

There are several advanced features that may be added to the cell definition:


A cell marked with an attribute "LEWIRE=1" denotes a wire load. There are two ways to specify the capacitance of an LEWIRE. The first is to use the LEWIRECAP attribute to specify the capacitance in fF. The second is to use two attributes "L" and "width" to specify the size of the wire - however this method has been deprecated because it unnecessarily complicates the defintion of the Wire Ratio setting.

The LEWIRECAP is converted to X size by the following formula:

X size = LEWIRECAP * wire_ratio / x1inverter_totalgate

In this case, "wire_ratio" is defined as lambda of gate per fF of wire capacitance. "x1inverter_totalgate" is the total lambda of gate of an X=1 inverter, which is defined as the sum of "x1inverter_nwidth" plus "x1inverter_pwidth" (see LEsettings).

Capacitors are likewise converted to X size by the formula:

X size = Capacitance / gate_cap / 1e-15 / x1inverter_totalgate


These commands may be given to the Logical Effort tool (in menu Tools / Logical Effort):

The LEsettings cell

There is a cell called LEsettings with the following attributes:

Prev Previous     Contents Table of Contents     Next Next