Electric VLSI Design System User's Manual

Chapter 9: Tools

9-8-2: Other Generators

There are other generators built into Electric. These commands (in menu Tool / Generation) may be used:

Coverage Implants Generator Although individual MOS nodes and arcs have the proper amount of implant around them, a collection of such objects may result in an irregular implant boundary. To clean this up, you can place pure-layer nodes of implant that neatly cover the implant area (see Section 7-1-1). This command does it automatically. It removes previous pieces of coverage implant before running, so that the result is a clean cover.
ROM Generator... The ROM generator constructs many cells to describe a ROM from a personality file. You will be prompted for the personality file. The first line of the ROM personality file lists the degree of folding. For example, a 256-word x 10-bit ROM with a folding degree of 4 will be implemented as a 64 x 40 array with 4:1 column multiplexors to return 10 bits of data while occupying more of a square form factor. The number of words and degree of folding should be a power of 2. The remaining lines of the file list the contents of each word. The parser is pretty picky. There should be a carriage return after the list word, but no other blank lines in the file. Here is a sample ROM file:
1 010101 011001 100101 101010 4 00000000 10000000 01000000 11000000
MOSIS CMOS PLA Generator... The MOSIS CMOS PLA generator reads two personality files (AND and OR) and generates a PLA array. Each file has only two numbers on the first line to define the size of the array, and the values of the array on subsequent lines. Both the AND file and the OR file are similar. Here is some sample PLA logic:
f = (a and b and (not c)) or ((not b) and (not a))

g = (a and c) or ((not a) and (not c))
Here is the AND file for the above logic:
4 3 1 1 0 0 0 X 1 X 1 0 X 0

Fill (MoCMOS)... Fill cells are used to meet metal density rules in modern fabrication processes by filling spaces with certain metal layers. Fill cells are also created to improve chip power distribution and to avoid voltage drops by inserting cap transistors. Electric has a coverage facility to evaluate the amount of fill (see Section 9-2-4). This command generates fill cells.

Unlike other fill generators, Electric's fill generator creates cells containing power and ground grids of specified layers, usually starting at Metal-2. These cells can also be arrayed into tile cells to cover larger areas. When Metal-1 is filled, the generator will cover the area with cap transistors whose functionality is to prevent voltage drops in the power grid.

The Fill dialog has two tabs: "Floorplan" and "Tiling". The Floorplan section specifies what is inside of a single fill cell. The Tiling section specifies how those cells are arrayed.

The Floorplan section offers two fill techniques: Template Fill and Fill Cell (not yet available). Template Fill generates fill cells of a given width and height. The default values reflect the minimum spacing rules given by the technology. The "Reserved Space" section lets you specify which layers of metal will be in the fill cells. These metal layers alternate running horizontally and vertically (the "Even layer orientation" controls which layer runs horizontally first).

The fill cell will have four metal wires running in each direction: the outer two are Ground and the inner two are Power. The spacing between the inner two is given in the "Vdd Space" section next to the selected metal layer. The spacing between the ground wires and the edge is half of the "Gnd Space" value. The spacing between the power and ground wires is the minimal design-rule spacing for that layer of metal. The width of the wires is then adjusted to fill the remaining space in the cell. Figure 9.62

Figure 9.61 The Tiling section lets you request arrays of fill cells to be generated. Check the desired sizes and they will be generated. Each generated array cell will contain the specified-size array, and it will be internally wired.

Generate gate layouts (MoCMOS) Generates the layout for schematic cells in the Purple and Red libraries (see Section 9-9). To use this command you must have a schematic in the current window. The command then hierarchically scans the schematic looking for instances of the Purple and Red library cells. When it finds such instances it generates layout for them and places the layout in a library called "autoGenLibMOCMOS". If the cell already exists, it is not regenerated.

The gate layout generator recognizes these gates from the Purple and Red libraries:

inv	mullerC_sy	nand2HTen	nms2K
inv2i	nand2	nand3	nms2_sy
inv2iKn	nand2HLT_sy	nand3LT	nms3_sy3
inv2iKp	nand2LT	nand3LT_sy3	nor2
invCLK	nand2LT_sy	nand3LTen	nor2kresetV
invCTLn	nand2PH	nand3MLT	pms1
invHT	nand2_sy	nand3en	pms1K
invK	nand2en	nms1	pms2
invLT	nand2k	nms1K	pms2_sy
inv_passgate	nand2LTen	nms2

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