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These are the tools available in Electric:
A hierarchical design-rule checker does a thorough check of the circuit.
Electric can also read the output of Assura or Calibre and display the results.
Users of Electric must obtain these simulators on their own.
The Pad Frame generator places pad cells around a chip core and wires them together.
The ROM generator produces layout from a ROM personality file.
The cell stitching router make explicit connections where cells abut or overlap.
The mimic router watches user activity.
When it sees a wire being created or deleted, it repeats the activity
in similar situations throughout the circuit.
The river router runs multiple parallel wires in a channel between cells.
The sea-of-gates router makes arbitrary connections in the circuit.
In addition, users are prevented from making changes to checked-out cells that would affect other
cells that are not checked-out.
Also, warnings are issued when multiple users check-out cells that are hierarchically related
which may cause interference in their editing.
A second project management system, based on CVS, writes each cell to a separate disk file
so CVS tools can manage the circuitry.
Design-Rule Checking
The incremental design-rule checker watches all changes made to the layout and displays error messages
when violations are detected.
It checks for spacing errors, notch errors, and minimum size violations.
Electrical-Rule Checking
The electrical-rule checker has two parts:
Simulation
Electric comes with a built-in 12-state switch-level simulator, called ALS.
An optional IRSIM simulation engine is available separately from Static Free Software.
The simulator displays waveforms in a separate window and lets users cross-probe from either
the waveform or the circuit window.
Simulation Interface
Electric is able to produce input decks for a number of popular simulators, including:
Generation
The CMOS PLA generator works from a library of PLA elements, thus allowing customized
arrays.
Compaction
The compactor adjusts geometry to its minimal spacing in the X and Y axes.
Logical Effort
Logical Effort is a system for marking digital schematic gates with fanout
information that will produce optimally fast circuits.
Routing
The maze router runs single wires between points.
VHDL
The VHDL system can generate VHDL from a layout, and can compile VHDL to netlists
of various format.
These netlists can then be simulated with the built-in simulator,
turned into layout with the silicon compiler,
or saved to disk for use by external simulators.
Silicon Compiler
The Silicon Compiler places and routes standard cells from a structural netlist (which can be
obtained from VHDL which can be obtained from a schematic drawing).
Network Consistency Checking (LVS)
The network consistency checker compares a layout with its equivalent schematic.
It can also compare two different versions of a layout or two different versions of a schematic.
An experimental version of NCC, called the Port Interchange Experiment, is also available.
Project Management
This built-in system allows users to share a library of circuitry.
Users can check out cells for editing and check them back in when done.
Other users are prevented from changing checked-out cells, and can have their
circuits updated when changes are checked in.