public class VerilogModel extends SimulationModel
Example:
Note that you need to call finish() to end the simulator. Also, devices can
only be created before the process is started.
// create a new VerilogModel
VerilogModel vm = new VerilogModel();
// create a jtag tester which connects to the given port names on the model
JtagTester jtag = vm.createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDOb");
// create a logic settable device to control the given port
LogicSettable enable = vm.createLogicSettable("enable");
// start the verilog process
vm.start("verilog", "chipModel.v", false);
....
vm.finish();
Modifier and Type | Field and Description |
---|---|
static int |
DUMPVARS
Use 'dumpvars' to record simulation
|
static java.lang.String |
jtagControllerFile |
static int |
NORECORD
Do not record simulation
|
static int |
RECORDVARS
Use 'recordvars' to record simulation
|
errorFlag, quitCommand, simulatorName
Constructor and Description |
---|
VerilogModel()
Create a new VerilogModel to simulate the behavior of the real chip.
|
Modifier and Type | Method and Description |
---|---|
JtagTester |
createJtagSubchainTester(java.lang.String jtagInBus,
java.lang.String jtagOutBus)
Create a subchain tester based on the 8- or 9-wire jtag interface.
|
JtagTester |
createJtagSubchainTester(java.lang.String phi2,
java.lang.String phi1,
java.lang.String write,
java.lang.String read,
java.lang.String sin,
java.lang.String sout)
Create a subchain tester based on the 5-wire jtag interface.
|
JtagTester |
createJtagTester(java.lang.String tckName,
java.lang.String tmsName,
java.lang.String trstbName,
java.lang.String tdiName,
java.lang.String tdobName)
Create a
JtagTester that can be used to drive the JtagController on the
Software model of the chip. |
LogicSettable |
createLogicSettable(java.util.List portNames)
Create a
LogicSettable that can be used to control a set of ports on
the Software model of the chip. |
LogicSettable |
createLogicSettable(java.lang.String portName)
Create a
LogicSettable that can be used to control a port on
the Software model of the chip. |
void |
disableNode(java.lang.String node)
If supported, disable a node (forces it to 0)
|
void |
enableNode(java.lang.String node)
If supported, enable a node (allows it to be driven)
|
int |
getNodeState(java.lang.String node)
Get the state of a node.
|
double |
getSimulationTime()
Get the current simulation time, used for error reporting
|
double |
getTimeNS()
Return the current simulation time in nanoseconds
|
double |
getVdd()
Get the voltage value for vdd
|
static void |
main(java.lang.String[] args)
Unit test
|
void |
releaseNode(java.lang.String s) |
void |
releaseNodes(java.util.List nodes)
Release any nodes being forced to a value using set node state
|
void |
setNodeState(java.lang.String node,
int state)
Force node to a state.
|
boolean |
start_(java.lang.String verilogCommand,
java.lang.String verilogSource,
int recordSim)
Start the Verilog process.
|
void |
wait(float seconds)
Let the verilog simulation run for some period of time.
|
void |
waitNS(double ns)
Wait for the specified number of nanoseconds.
|
void |
waitPS(double ps)
Wait for the specified number of picoseconds.
|
void |
waitTicks(long ticks)
Let the verilog simulation for some number of verilog ticks.
|
assertNodeState, assertNodeState, createJtagTester, finish, finishAll, getElapsedTime, getNodeState, getOptimizedDirectReadsWrites, isBypassScanning, isProcessRunning, issueCommand, issueCommand, setAdditionalCommandLineArgs, setBypassScanning, setNodeState, setOptimizedDirectReadsWrites, setPrompt, start, start, startProcess, waitSeconds
public static final int NORECORD
public static final int DUMPVARS
public static final int RECORDVARS
public static final java.lang.String jtagControllerFile
public VerilogModel()
public JtagTester createJtagTester(java.lang.String tckName, java.lang.String tmsName, java.lang.String trstbName, java.lang.String tdiName, java.lang.String tdobName)
SimulationModel
JtagTester
that can be used to drive the JtagController on the
Software model of the chip. The arguments specify the port names specific
to the software model that correspond to the Jtag Controller ports.createJtagTester
in class SimulationModel
tckName
- name of the input port for TCKtmsName
- name of the input port for TMStrstbName
- name of the input port for TRSTbtdiName
- name of the input port for TDItdobName
- name of the input port for TDObpublic JtagTester createJtagSubchainTester(java.lang.String jtagInBus, java.lang.String jtagOutBus)
SimulationModel
createJtagSubchainTester
in class SimulationModel
jtagInBus
- the name of the 9-bit wide input bus, i.e. "jtagIn" or "jtagIn[8:0]"jtagOutBus
- the name of the 9-bit wide output bus, i.e. "jtagOut" or "jtagOut[8:0]"public JtagTester createJtagSubchainTester(java.lang.String phi2, java.lang.String phi1, java.lang.String write, java.lang.String read, java.lang.String sin, java.lang.String sout)
SimulationModel
createJtagSubchainTester
in class SimulationModel
phi2
- name of the phi2 signalphi1
- name of the phi1 signalwrite
- name of the write signalread
- name of the read signalsin
- name of the scan data in signalsout
- name of the scan data out signalpublic LogicSettable createLogicSettable(java.lang.String portName)
SimulationModel
LogicSettable
that can be used to control a port on
the Software model of the chip.createLogicSettable
in class SimulationModel
portName
- the name of the port to control.public LogicSettable createLogicSettable(java.util.List portNames)
SimulationModel
LogicSettable
that can be used to control a set of ports on
the Software model of the chip. The ports then act as if they have
been tied together.createLogicSettable
in class SimulationModel
portNames
- a list of Strings of port names to be controlled.public void disableNode(java.lang.String node)
SimulationModel
disableNode
in class SimulationModel
node
- the name of the nodepublic void enableNode(java.lang.String node)
SimulationModel
enableNode
in class SimulationModel
node
- the name of the nodepublic double getVdd()
SimulationModel
getVdd
in class SimulationModel
public double getSimulationTime()
SimulationModel
getSimulationTime
in class SimulationModel
public boolean start_(java.lang.String verilogCommand, java.lang.String verilogSource, int recordSim)
1. Create a local copy of the test harness file with information specific to this chip, and test setup.
2. Setup input/output streams for talking to/from the verilog process.
3. Run the verilog process on the local test harness file.
verilogCommand
- the command to run Verilog.verilogSource
- the chip netlist.recordSim
- true to record simulation via $recordfile(), $recordvars; false to not do so.public void wait(float seconds)
wait
in interface ChipModel
wait
in class SimulationModel
seconds
- public void waitNS(double ns)
ChipModel
waitNS
in interface ChipModel
waitNS
in class SimulationModel
ns
- the number of nanoseconds to wait.public void waitPS(double ps)
ChipModel
waitPS
in interface ChipModel
waitPS
in class SimulationModel
ps
- the number of picoseconds to wait.public void waitTicks(long ticks)
ticks
- public double getTimeNS()
SimulationModel
getTimeNS
in class SimulationModel
public void setNodeState(java.lang.String node, int state)
setNodeState
in class SimulationModel
node
- the hierarchical spice node namestate
- the state to set to, must be 1 or 0.public int getNodeState(java.lang.String node)
getNodeState
in class SimulationModel
node
- the hierarchical spice node namepublic void releaseNode(java.lang.String s)
public void releaseNodes(java.util.List nodes)
SimulationModel
releaseNodes
in class SimulationModel
nodes
- a list of node names (strings)public static void main(java.lang.String[] args)