Package | Description |
---|---|
com.sun.electric.tool.simulation.test |
Chip-independent test software library for the
Asynchronous Design Group in Oracle Labs, see bottom
for locations of documentation.
|
Modifier and Type | Class and Description |
---|---|
class |
BypassJtagTester
Parent class for simulation jtag testers.
|
class |
JtagSubchainTesterModel |
class |
JtagTesterModel |
class |
MockJtag
Mock up of the control of a
Netscan JTAG tester, allows
simulated execution of test software even in the absence of a chip. |
class |
NanosimJtag
Parent class for
NanosimJtagTester and NanosimJtagSubchainTester . |
class |
NanosimJtagSubchainTester
Control a section of a scan chain
|
class |
NanosimJtagTester |
class |
Netscan
Initialization, configuration, and connection API for Corelis NET-1149.1/E
one-port boundary scan controller (JTAG tester device).
|
class |
Netscan4
Connection and reset API for a single port on the Corelis NETUSB-1149.1/E
four-port boundary scan controller (JTAG tester device).
|
class |
NetscanGeneric
Generic initialization, configuration, and connection API for Corelis
boundary scan controllers (JTAG testers).
|
class |
Signalyzer |
class |
VerilogJtagSubchainTester
Control a section of a scan chain
|
class |
VerilogJtagTester
A JtagTester that interfaces with a verilog model of the Device Under Test.
|
Modifier and Type | Method and Description |
---|---|
JtagTester |
VerilogModel.createJtagSubchainTester(java.lang.String jtagInBus,
java.lang.String jtagOutBus) |
abstract JtagTester |
SimulationModel.createJtagSubchainTester(java.lang.String jtagInBus,
java.lang.String jtagOutBus)
Create a subchain tester based on the 8- or 9-wire jtag interface.
|
JtagTester |
NanosimModel.createJtagSubchainTester(java.lang.String jtagInBus,
java.lang.String jtagOutBus)
Create a subchain tester based on the 8- or 9-wire jtag interface.
|
JtagTester |
VerilogModel.createJtagSubchainTester(java.lang.String phi2,
java.lang.String phi1,
java.lang.String write,
java.lang.String read,
java.lang.String sin,
java.lang.String sout) |
abstract JtagTester |
SimulationModel.createJtagSubchainTester(java.lang.String phi2,
java.lang.String phi1,
java.lang.String write,
java.lang.String read,
java.lang.String sin,
java.lang.String sout)
Create a subchain tester based on the 5-wire jtag interface.
|
JtagTester |
NanosimModel.createJtagSubchainTester(java.lang.String phi2,
java.lang.String phi1,
java.lang.String write,
java.lang.String read,
java.lang.String sin,
java.lang.String sout)
Create a subchain tester based on the 5-wire jtag interface.
|
JtagTester |
SimulationModel.createJtagTester()
Create a
JtagTester that can be used to drive the JtagController on the
Software model of the chip. |
JtagTester |
VerilogModel.createJtagTester(java.lang.String tckName,
java.lang.String tmsName,
java.lang.String trstbName,
java.lang.String tdiName,
java.lang.String tdobName) |
abstract JtagTester |
SimulationModel.createJtagTester(java.lang.String tckName,
java.lang.String tmsName,
java.lang.String trstbName,
java.lang.String tdiName,
java.lang.String tdobName)
Create a
JtagTester that can be used to drive the JtagController on the
Software model of the chip. |
JtagTester |
NanosimModel.createJtagTester(java.lang.String tckName,
java.lang.String tmsName,
java.lang.String trstbName,
java.lang.String tdiName,
java.lang.String tdobName) |
JtagTester |
ChainControl.getJtag()
Returns device-independent JTAG tester object
|
Constructor and Description |
---|
ChainControl(java.lang.String fileName,
JtagTester jtagTester,
float jtagVolts,
int jtagKhz)
Creates an object to program scan chains using the boundary scan
controller
jtagTester and assuming the scan chain
hierarchy specified in the XML file fileName . |
ChainControlFake(java.lang.String chipName,
int lengthIR,
JtagTester jtagTester,
float jtagVolts,
int jtagKhz) |
JtagLogicLevel(JtagTester jtag,
int index)
Creates a
LogicSettable that controls a single parallel
output or GPIO pin on the TAP connector for a JTAG tester port. |