Package | Description |
---|---|
com.sun.electric.tool.simulation.test |
Chip-independent test software library for the
Asynchronous Design Group in Oracle Labs, see bottom
for locations of documentation.
|
Modifier and Type | Class and Description |
---|---|
class |
JtagLogicLevel
Settable logic level provided by a single pin on one port of a JTAG tester.
|
class |
LogicLevel
Class for setting Vdd and a logic level on a chip, when both values are
provided by power supplies.
|
class |
NanosimLogicSettable |
class |
VerilogLogicSettable
A Logic Settable device that interfaces with a verilog simulation.
|
Modifier and Type | Method and Description |
---|---|
LogicSettable |
VerilogModel.createLogicSettable(java.util.List portNames) |
abstract LogicSettable |
SimulationModel.createLogicSettable(java.util.List portNames)
Create a
LogicSettable that can be used to control a set of ports on
the Software model of the chip. |
LogicSettable |
NanosimModel.createLogicSettable(java.util.List portNames) |
LogicSettable |
VerilogModel.createLogicSettable(java.lang.String portName) |
abstract LogicSettable |
SimulationModel.createLogicSettable(java.lang.String portName)
Create a
LogicSettable that can be used to control a port on
the Software model of the chip. |
LogicSettable |
NanosimModel.createLogicSettable(java.lang.String portName) |