public class CompileVerilogStruct
extends java.lang.Object
Modifier and Type | Class and Description |
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static class |
CompileVerilogStruct.VExport
Class to define ports on Verilog Modules.
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static class |
CompileVerilogStruct.VInstance
Class to define an instance or transistor, found inside of a Verilog module.
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class |
CompileVerilogStruct.VModule
Class to define a Verilog Module (or Primitive)
|
static class |
CompileVerilogStruct.VPort
Class to define a port on a VInstance.
|
Constructor and Description |
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CompileVerilogStruct(Cell verilogCell,
boolean verbose)
The constructor compiles the Verilog in a Verilog-view Cell.
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CompileVerilogStruct(java.io.File f,
boolean verbose,
ErrorLogger logger)
The constructor compiles the Verilog in disk file.
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CompileVerilogStruct(java.lang.String[] strings,
boolean verbose)
The constructor compiles the Verilog in an array of Strings.
|
Modifier and Type | Method and Description |
---|---|
Cell |
genCell(Library destLib,
boolean schematic,
EditingPreferences ep,
IconParameters ip)
Method to generate a cell that represents this netlist.
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java.util.List<java.lang.String> |
getALSNetlist(Library destLib)
Method to generate an ALS (simulation) netlist.
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java.util.List<CompileVerilogStruct.VModule> |
getModules()
Method to return a list of Verilog Modules.
|
java.util.List<java.lang.String> |
getQUISCNetlist(Library destLib,
boolean isIncludeDateAndVersionInOutput)
Method to generate a QUISC (silicon compiler) netlist.
|
boolean |
hadErrors()
Method to report the validity of the Verilog.
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boolean |
hasErrors()
Method to report whether the Verilog compile was successful.
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public CompileVerilogStruct(java.io.File f, boolean verbose, ErrorLogger logger)
f
- the disk file.verbose
- true to give progress while compiling.public CompileVerilogStruct(Cell verilogCell, boolean verbose)
verilogCell
- the Cell with the Verilog text.verbose
- true to give progress while compiling.public CompileVerilogStruct(java.lang.String[] strings, boolean verbose)
strings
- the Verilog text.verbose
- true to give progress while compiling.public boolean hadErrors()
public java.util.List<CompileVerilogStruct.VModule> getModules()
public boolean hasErrors()
public Cell genCell(Library destLib, boolean schematic, EditingPreferences ep, IconParameters ip)
destLib
- destination library.schematic
- true to make schematics; false for layoutpublic java.util.List<java.lang.String> getALSNetlist(Library destLib)
destLib
- destination library.public java.util.List<java.lang.String> getQUISCNetlist(Library destLib, boolean isIncludeDateAndVersionInOutput)
destLib
- destination library.isIncludeDateAndVersionInOutput
- include date and version in output