Package | Description |
---|---|
com.sun.electric.tool.simulation.test |
Chip-independent test software library for the
Asynchronous Design Group in Oracle Labs, see bottom
for locations of documentation.
|
Class and Description |
---|
AmpsVsVolts
Measures current as a function of voltage, writing results to file.
|
BERT
Interface for a HP81250 Bit Error Rate Tester.
|
BERT.DataAnalyzer
A Data Analyzer is a terminal that acquires/analyzes data.
|
BERT.DataGenerator
A Data Generator is a terminal that generates data
|
BERT.DataModule
A Data Generator/Analyzer Module.
|
BERT.SignalMode |
BERT.Terminal
A Terminal drives or reads a signal to or from a
chip.
|
BitVector
Provides a fixed-length bit vector and methods for acting on it.
|
BussedIO |
BypassJtagTester
Parent class for simulation jtag testers.
|
ChainControl
Main API for scan chain programming, provides control of a single port on a
JTAG tester.
|
ChainNode
Represents an entire scan chain, covering all of the scan chain elements at a
single address on the chip's JTAG controller.
|
ChainNode.ShiftListener |
ChipModel
The ChipModel is meant to abstract the underlying device under test.
|
CurrentReadable
Device-independent interface to something (e.g., power supply or digitial
multimeter) that can read back current
|
Equipment
Device-independent control of a piece of experimental equipment over GPIB.
|
EquipmentInterface
Equipment implements only a GPIB equipment.
|
JtagSubchainTesterModel |
JtagTester
Device-independent control of a single port on a JTAG tester.
|
JtagTesterModel |
Logger
Provides user-configurable diagnostic messages to device classes that extend
this class.
|
LogicSettable
Generic interface for setting logic levels for outputs to chip
|
MyTreeNode
Default node class for chip-testing hierarchical data structures.
|
Name
A Name is a text-parsing object for port, node and arc names.
|
NanosimBERT.Event
An Event to send to the Nanosim Simulator,
the same as the BERT would transition a signal
and send that to the real chip.
|
NanosimBERT.NanosimDataModule |
NanosimBERT.NanosimTerminal |
NanosimDataAnalyzer |
NanosimModel |
NetscanGeneric
Generic initialization, configuration, and connection API for Corelis
boundary scan controllers (JTAG testers).
|
PowerChannel
Abstract class allowing generic control of a single power supply channel,
independent of the nature of the power supply.
|
SimulationModel
Defines a model that replaces the actual chip (device under test).
|
SubchainNode
Represent a single node of a scan chain.
|
SubchainNode.DataNet |
VoltageReadable
Device-independent interface to something (e.g., power supply or
digitial multimeter) that can read back voltage
|