Technology fpga
class com.sun.electric.technology.technologies.FPGA
shortName=FPGA
techDesc=FPGA Building-Blocks
Bits:  NONSTANDARD STATICTECHNOLOGY NOPRIMTECHNOLOGY
isScaleRelevant=truefpga.Scale=2000.0(2000.0)
fpga.Foundry=NONE(NONE)
fpga.NumMetalLayers=1(1)
fpga.MininumResistance=10.0(10.0)
fpga.GateLengthSubtraction=0.0(0.0)
fpga.Gate Inclusion=false(false)
fpga.Ground Net Inclusion=false(false)
fpga.MaxSeriesResistance=10.0(10.0)
fpga.LogicalEffort.GateCapacitance=0.4(0.4)
fpga.LogicalEffort.WireRatio=0.16(0.16)
fpga.LogicalEffort.DiffAlpha=0.7(0.7)
ResolutionValueForfpga=0.0
Layer Wire METAL1
	fpga.CIF.Wire=()
	fpga.DXF.Wire=()
	fpga.Skill.Wire=()
	fpga.Resistance.Wire=0.0(0.0)
	fpga.Capacitance.Wire=0.0(0.0)
	fpga.EdgeCapacitance.Wire=0.0(0.0)
	patternedOnDisplay=false(false)
	patternedOnPrinter=false(false)
	outlined=None(None)
	transparent=0(0)
	color=ffff0000(ff0000)
	opacity=1.0(1.0)
	foreground=true
	pattern 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
	distance3D=0.0
	thickness3D=0.0
	mode3D=NONE
	factor3D=0.0
Layer Component ART
	fpga.CIF.Component=()
	fpga.DXF.Component=()
	fpga.Skill.Component=()
	fpga.Resistance.Component=0.0(0.0)
	fpga.Capacitance.Component=0.0(0.0)
	fpga.EdgeCapacitance.Component=0.0(0.0)
	patternedOnDisplay=false(false)
	patternedOnPrinter=false(false)
	outlined=None(None)
	transparent=0(0)
	color=ff000000(0)
	opacity=1.0(1.0)
	foreground=true
	pattern 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
	distance3D=0.0
	thickness3D=0.0
	mode3D=NONE
	factor3D=0.0
Layer Pip ART
	fpga.CIF.Pip=()
	fpga.DXF.Pip=()
	fpga.Skill.Pip=()
	fpga.Resistance.Pip=0.0(0.0)
	fpga.Capacitance.Pip=0.0(0.0)
	fpga.EdgeCapacitance.Pip=0.0(0.0)
	patternedOnDisplay=false(false)
	patternedOnPrinter=false(false)
	outlined=None(None)
	transparent=0(0)
	color=ff00ff00(ff00)
	opacity=1.0(1.0)
	foreground=true
	pattern 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
	distance3D=0.0
	thickness3D=0.0
	mode3D=NONE
	factor3D=0.0
Layer Repeater ART
	fpga.CIF.Repeater=()
	fpga.DXF.Repeater=()
	fpga.Skill.Repeater=()
	fpga.Resistance.Repeater=0.0(0.0)
	fpga.Capacitance.Repeater=0.0(0.0)
	fpga.EdgeCapacitance.Repeater=0.0(0.0)
	patternedOnDisplay=false(false)
	patternedOnPrinter=false(false)
	outlined=None(None)
	transparent=0(0)
	color=ff0000ff(ff)
	opacity=1.0(1.0)
	foreground=true
	pattern 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
	distance3D=0.0
	thickness3D=0.0
	mode3D=NONE
	factor3D=0.0
ArcProto wire metal-1
	isWipable=false
	isCurvable=false
	isSpecialArc=false
	isEdgeSelect=false
	isNotUsed=false
	isSkipSizeInPalette=false
	DefaultExtendForwireINfpga=0.0
	baseExtend=0.0
	defaultLambdaBaseWidth=0.0
	diskOffset1=0.0
	diskOffset2=0.0
	DefaultAngleForwireINfpga=45
	DefaultRigidForwireINfpga=false
	DefaultFixedAngleForwireINfpga=true
	DefaultExtendedForwireINfpga=true
	DefaultDirectionalForwireINfpga=false
		arcLayer layer=Wire style=FILLED extend=0.0
PrimitiveNode Wire_Pin pin NSQUARE WIPEON1OR2
	specialType=0 numMultiCuts=0
	SizeOffset {X:[0.0,0.0] Y:[0.0,0.0]}
	fullRectangle=ERectangle[x=-0.5,y=-0.5,w=1.0,h=1.0]
	baseRectangle=ERectangle[x=-0.5,y=-0.5,w=1.0,h=1.0]
	DefaultExtendXForWire_PinINfpga=0.0
	DefaultExtendYForWire_PinINfpga=0.0
	diskOffset1=0.5,0.5
	diskOffset2=0.5,0.5
	layers:
	layer=Wire port=0 style=DISC repr=0
		point xm=0.0 xa=0.0 ym=0.0 ya=0.0
		point xm=0.5 xa=0.0 ym=0.0 ya=0.0
	port wire angle=0 range=180 topology=0 unknown
		lm=0.0 la=0.0 rm=0.0 ra=0.0 bm=0.0 ba=0.0 tm=0.0 ta=0.0
		isolated=false negatable=false
		portArc wire
		portArc Universal
		portArc Invisible
		portArc Unrouted
PrimitiveNode Pip connection NSQUARE
	specialType=0 numMultiCuts=0
	SizeOffset {X:[0.0,0.0] Y:[0.0,0.0]}
	fullRectangle=ERectangle[x=-1.0,y=-1.0,w=2.0,h=2.0]
	baseRectangle=ERectangle[x=-1.0,y=-1.0,w=2.0,h=2.0]
	DefaultExtendXForPipINfpga=0.0
	DefaultExtendYForPipINfpga=0.0
	diskOffset1=1.0,1.0
	diskOffset2=1.0,1.0
	layers:
	layer=Pip port=0 style=FILLED repr=1
		point xm=-0.5 xa=0.0 ym=-0.5 ya=0.0
		point xm=0.5 xa=0.0 ym=0.5 ya=0.0
	port pip angle=0 range=180 topology=0 unknown
		lm=0.0 la=0.0 rm=0.0 ra=0.0 bm=0.0 ba=0.0 tm=0.0 ta=0.0
		isolated=false negatable=false
		portArc wire
		portArc Universal
		portArc Invisible
		portArc Unrouted
PrimitiveNode Repeater connection
	specialType=0 numMultiCuts=0
	SizeOffset {X:[0.0,0.0] Y:[0.0,0.0]}
	fullRectangle=ERectangle[x=-5.0,y=-1.5,w=10.0,h=3.0]
	baseRectangle=ERectangle[x=-5.0,y=-1.5,w=10.0,h=3.0]
	DefaultExtendXForRepeaterINfpga=0.0
	DefaultExtendYForRepeaterINfpga=0.0
	diskOffset1=5.0,1.5
	diskOffset2=5.0,1.5
	layers:
	layer=Repeater port=0 style=FILLED repr=1
		point xm=-0.5 xa=0.0 ym=-0.5 ya=0.0
		point xm=0.5 xa=0.0 ym=0.5 ya=0.0
	port a angle=180 range=45 topology=0 unknown
		lm=-0.5 la=0.0 rm=-0.5 ra=0.0 bm=0.0 ba=0.0 tm=0.0 ta=0.0
		isolated=false negatable=false
		portArc wire
		portArc Universal
		portArc Invisible
		portArc Unrouted
	port b angle=0 range=45 topology=1 unknown
		lm=0.5 la=0.0 rm=0.5 ra=0.0 bm=0.0 ba=0.0 tm=0.0 ta=0.0
		isolated=false negatable=false
		portArc wire
		portArc Universal
		portArc Invisible
		portArc Unrouted
Foundry NONE
	fpga.GDS.Wire=()
	fpga.GDS.Component=()
	fpga.GDS.Pip=()
	fpga.GDS.Repeater=()
 menu 0 0 arc wire
 menu 1 0 Cell
 menu 2 0 Misc.
 menu 3 0 Pure
 menu 4 0 nodeInst Wire_Pin:pin:
 menu 5 0 node Pip
 menu 6 0 node Repeater
    <Foundry name="NONE">
    </Foundry>
