/* Verilog for cell 'VerilogTest3{sch}' from library 'netlistTests' */
/* Written by Electric VLSI Design System */

module netlistTests__VerilogTest3Low(leaf, root);
  inout [8:1] leaf;
  inout [5:1] root;

endmodule   /* netlistTests__VerilogTest3Low */

module VerilogTest3(leaf);
  inout [8:1] leaf;

  wire [5:1] a;

  netlistTests__VerilogTest3Low JTAGamp_0(.leaf(leaf[8:1]), .root(a[5:1]));
endmodule   /* VerilogTest3 */
