/* Verilog for cell 'VerilogTest6WithVeryLongNameNowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty-1-nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty-2{lay}' from library 'netlistTests' */
/* Written by Electric VLSI Design System */

module 
      VerilogTest6WithVeryLongNameNowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_1_nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_2(
      nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_A_nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_B)
      ;
  input 
      nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_A_nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_B;

  wire nmos_0_diff_bottom, nmos_0_diff_top;

  tranif1 nmos_0(nmos_0_diff_top, nmos_0_diff_bottom, 
      nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_A_nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_B)
      ;
endmodule   /* VerilogTest6WithVeryLongNameNowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_1_nowIsTheTimeForAllGoodMenToComeToTheAidOfTheParty_2 */
