/* Verilog for cell 'VerilogTest5{sch}' from library 'netlistTests' */
/* Written by Electric VLSI Design System */

module netlistTests__VerilogTest5Lower(a, b, y);
  input a;
  input b;
  output y;

  wire and_0_yc, and_0_yt;

  and and_0(y, a, b);
endmodule   /* netlistTests__VerilogTest5Lower */

module VerilogTest5(m, z, a);
  input [0:3] m;
  input [0:3] z;
  input a;

  wire buf_0_c, net_6, or_0_yc, or_0_yt, xor_0_yc, xor_0_yt;
  wire [0:3] d;

  /* user-specified Verilog declarations */
  wire b, c;
  wire e, f;

  /* user-specified Verilog code */
  a = b + c;
  b = e - f;

  /* automatically generated Verilog */
  not buf_0(z[1], net_6);
  or or_0(net_6, a, z[3], z[2]);
  xor xor_0(z[0], a, z[3]);
  netlistTests__VerilogTest5Lower and_0_(.a(m[0]), .b(z[0]), .y(d[0]));
  netlistTests__VerilogTest5Lower and_1_(.a(m[1]), .b(z[1]), .y(d[1]));
  netlistTests__VerilogTest5Lower and_2_(.a(m[2]), .b(z[2]), .y(d[2]));
  netlistTests__VerilogTest5Lower and_3_(.a(m[3]), .b(z[3]), .y(d[3]));
endmodule   /* VerilogTest5 */
