VERSION  5.2 ;
NAMESCASESENSITIVE ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS  "[]" ;
DESIGN regCell_0_0 ;
UNITS DISTANCE MICRONS 1000 ;

HISTORY CREATETIME 6-Aug-99 16:10:55 ;
HISTORY SAVETIME 10-Aug-99 10:18:57 ;
HISTORY DB CREATE by rkao ;
HISTORY Name: LBRARY, dir: '' ;
HISTORY SE version: 5.2.9 MASTER, DB code version: 5.1, DB created under: 5.1 ;
HISTORY Max mem: 25165824, mainsail: $CDS_INST_DIR/tools/dsm/lib/sys1410r.olb:
        14.10 ;
HISTORY System no. 19 --> SPARC UNIX, CPU id = 'Sun_Microsystems: 2157134407' ;
HISTORY Design saved as LBRARY in directory  ;
HISTORY DB LOAD by rkao ;
HISTORY Name: LBRARY, dir: '' ;
HISTORY SE version: 5.2.9 MASTER, DB code version: 5.1, DB created under: 5.1 ;
HISTORY Max mem: 25165824, mainsail: $CDS_INST_DIR/tools/dsm/lib/sys1410r.olb:
        14.10 ;
HISTORY System no. 19 --> SPARC UNIX, CPU id = 'Sun_Microsystems: 2157134407' ;
HISTORY Design saved as /export/home/rkao/test/regfile/PLAID/plaid/clef/clef in
        directory  ;
HISTORY DB LOAD by rkao ;
HISTORY Name: /export/home/rkao/test/regfile/PLAID/plaid/clef/clef, dir: '' ;
HISTORY SE version: 5.2.9 MASTER, DB code version: 5.1, DB created under: 5.1 ;
HISTORY Max mem: 524288000, mainsail: $CDS_INST_DIR/tools/dsm/lib/sys1410r.olb:
        14.10 ;
HISTORY System no. 19 --> SPARC UNIX, CPU id = 'Sun_Microsystems: 2157134407' ;
HISTORY INPUT VERILOG FILENAME "../../../../plaid/physrc/regCell_0_0.v" LIB
        "designLib" REFLIB "stdCellLib" DESIGN " designLib.regCell_0_0:hdl" ;
HISTORY OUTPUT DEF FILENAME "regCell_0_0.def" ;
HISTORY Design saved as regCell_0_0 in directory  ;
HISTORY DB LOAD by rkao ;
HISTORY Name: ../../../../plaid/physical/regCell_0_0/base/regCell_0_0, dir: '' ;
HISTORY SE version: 5.2.9 MASTER, DB code version: 5.1, DB created under: 5.1 ;
HISTORY Max mem: 524288000, mainsail: $CDS_INST_DIR/tools/dsm/lib/sys1410r.olb:
        14.10 ;
HISTORY System no. 19 --> SPARC UNIX, CPU id = 'Sun_Microsystems: 2157134407' ;
HISTORY INPUT DEF FILENAME "../placed/regCell_0_0.placed.def" ;
HISTORY OUTPUT DEF FILENAME "../placed/regCell_0_0.def" ;
HISTORY WROUTE ;
HISTORY OUTPUT LEF BLOCK FILENAME "regCell_0_0.lef.tmp" SIZE 9600 22000 PINMAP
        "vdd!" = "VDD" , "gnd!" = "VSS" , "re0" = "re0" , "re1" = "re1" , "we" =
        "we" , "dout0" = "dout0" , "dout1" = "dout1" , "din" = "din" ;
HISTORY Design saved as regCell_0_0 in directory  ;


PROPERTYDEFINITIONS
DESIGN  VERILOGDESIGNNAME  STRING  "designLib.regCell_0_0:hdl"  ;

END PROPERTYDEFINITIONS
DIEAREA ( 0 0 ) ( 9600 22000 ) ;

ROW ROW_1 tsm1site 0 11000 N DO 12 BY 1 STEP 800 8000 ;
ROW ROW_0 tsm1site 0 0 N DO 12 BY 1 STEP 800 8000 ;
TRACKS Y 500 DO 23 STEP 1000 LAYER METAL1 METAL2 ;
TRACKS Y 500 DO 23 STEP 1000 LAYER METAL2 METAL3 METAL4 ;
TRACKS Y 500 DO 23 STEP 1000 LAYER METAL4 METAL5 ;
TRACKS X 400 DO 13 STEP 800 LAYER METAL1 METAL2 METAL3 ;
TRACKS X 400 DO 13 STEP 800 LAYER METAL3 METAL4 METAL5 ;
GCELLGRID Y 0 DO 4 STEP 8000 ;
GCELLGRID Y 0 DO 1 STEP 0 ;
GCELLGRID X 0 DO 3 STEP 10000 ;
GCELLGRID X 0 DO 1 STEP 0 ;

VIAS 4 ;
- via4 + RECT METAL5 ( -270 -270 ) ( 270 270 ) + RECT VIA45 ( -180 -180 )
  ( 180 180 ) + RECT METAL4 ( -200 -270 ) ( 200 270 ) ;
- via3 + RECT METAL4 ( -200 -270 ) ( 200 270 ) + RECT VIA34 ( -180 -180 )
  ( 180 180 ) + RECT METAL3 ( -200 -270 ) ( 200 270 ) ;
- via2 + RECT METAL3 ( -200 -270 ) ( 200 270 ) + RECT VIA23 ( -180 -180 )
  ( 180 180 ) + RECT METAL2 ( -200 -270 ) ( 200 270 ) ;
- via1 + RECT METAL2 ( -200 -270 ) ( 200 270 ) + RECT VIA12 ( -180 -180 )
  ( 180 180 ) + RECT METAL1 ( -200 -270 ) ( 200 270 ) ;
END VIAS

COMPONENTS 3 ;
- dout1_tri TBUFIX1 + PLACED ( 0 11000 ) N ;
- dout0_tri TBUFIX1 + PLACED ( 4000 11000 ) N ;
- q_reg TLATX1 + PLACED ( 0 0 ) N ;
END COMPONENTS

PINS 8 ;
- gnd! + NET gnd! + DIRECTION INPUT + USE GROUND ;
- vdd! + NET vdd! + DIRECTION INPUT + USE POWER ;
- re1 + NET re1 + DIRECTION INPUT + USE SIGNAL + LAYER METAL3 ( -200 0 ) ( 200
  9600 ) + PLACED ( 0 10500 ) E ;
- re0 + NET re0 + DIRECTION INPUT + USE SIGNAL + LAYER METAL3 ( -200 0 ) ( 200
  9600 ) + PLACED ( 0 4500 ) E ;
- we + NET we + DIRECTION INPUT + USE SIGNAL + LAYER METAL3 ( -200 0 ) ( 200
  9600 ) + PLACED ( 0 15500 ) E ;
- din + NET din + DIRECTION INPUT + USE SIGNAL + LAYER METAL4 ( -200 0 ) ( 200
  22000 ) + PLACED ( 8400 0 ) N ;
- dout1 + NET dout1 + DIRECTION OUTPUT + USE SIGNAL + LAYER METAL4 ( -200 0 ) (
  200 22000 ) + PLACED ( 5200 0 ) N ;
- dout0 + NET dout0 + DIRECTION OUTPUT + USE SIGNAL + LAYER METAL4 ( -200 0 ) (
  200 22000 ) + PLACED ( 2800 0 ) N ;
END PINS

SPECIALNETS 2 ;
- gnd! ( q_reg VSS ) ( dout0_tri VSS ) ( dout1_tri VSS ) + USE GROUND ;
- vdd! ( q_reg VDD ) ( dout0_tri VDD ) ( dout1_tri VDD ) + USE POWER ;
END SPECIALNETS

NETS 7 ;
- we ( PIN we ) ( q_reg G )
  + ROUTED METAL3 ( 1200 15500  ) via2 ( * 9500  ) via1 ( 400 *  ) via1 ( * 4500
   ) via1 ;
- din ( PIN din ) ( q_reg D )
  + ROUTED METAL4 ( 8400 5500  ) via3 ( 2000 *  ) via2 ( * 4500  ) via1 ;
- re0 ( PIN re0 ) ( dout0_tri OE )
  + ROUTED METAL3 ( 4400 4500  ) via2 ( * 14500  ) via1 ;
- dout0 ( PIN dout0 ) ( dout0_tri Y )
  + ROUTED METAL1 ( 7600 13500  ) via1 ( * 12500  ) via2 ( 2800 *  ) via3 ;
- re1 ( PIN re1 ) ( dout1_tri OE )
  + ROUTED METAL3 ( 400 10500  ) via2 ( * 14500  ) via1 ;
- n123 ( q_reg QN ) ( dout0_tri A ) ( dout1_tri A )
  + ROUTED METAL1 ( 6000 14500  ) via1 ( * 9500  ) via1 ( 9200 *  ) via1
  ( * 5500  ) via1
  NEW METAL1 ( 2000 14500  ) via1 ( * 16500  ) via1 ( 6000 *  ) via1 ( * 14500
   ) ;
- dout1 ( PIN dout1 ) ( dout1_tri Y )
  + ROUTED METAL1 ( 3600 15500  ) via1 ( * 16500  ) via2 ( 5200 *  ) via3 ;
END NETS

END DESIGN
