/* Verilog for cell 'VerilogTest2{sch}' from library 'netlistTests' */
/* Written by Electric VLSI Design System */

module netlistTests__VerilogTest2Low( \s[1] , \s[2] , \s[4] , \s[5] );
  input \s[1] , \s[2] , \s[4] , \s[5] ;

endmodule   /* netlistTests__VerilogTest2Low */

module VerilogTest2(S);
  input [1:5] S;

  netlistTests__VerilogTest2Low low2_0(.\s[1] (S[1]), .\s[2] (S[2]), .\s[4] 
      (S[4]), .\s[5] (S[5]));
  netlistTests__VerilogTest2Low low2_1(.\s[1] (S[1]), .\s[2] (S[2]), .\s[4] 
      (S[4]), .\s[5] (S[5]));
endmodule   /* VerilogTest2 */
