/* Verilog for cell 'VerilogTest1{sch}' from library 'netlistTests' */
/* Written by Electric VLSI Design System */

module netlistTests__VerilogTest1LowA(a, w);
  input [9:0] a;
  input w;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(a[0], gnd, w);
  tranif1 nmos_1(a[2], gnd, w);
  tranif1 nmos_2(a[4], gnd, w);
  tranif1 nmos_3(a[6], gnd, w);
  tranif1 nmos_4(a[8], gnd, w);
  tranif0 nmos_5(a[3], vdd, w);
  tranif0 nmos_6(a[5], vdd, w);
  tranif0 nmos_7(a[7], vdd, w);
  tranif0 nmos_8(a[9], vdd, w);
  tranif0 pmos_0(a[1], vdd, w);
endmodule   /* netlistTests__VerilogTest1LowA */

module netlistTests__VerilogTest1LowB(w, a);
  input w;
  output [0:9] a;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(a[0], gnd, w);
  tranif1 nmos_1(a[2], gnd, w);
  tranif1 nmos_2(a[4], gnd, w);
  tranif1 nmos_3(a[6], gnd, w);
  tranif1 nmos_4(a[8], gnd, w);
  tranif0 nmos_5(a[3], vdd, w);
  tranif0 nmos_6(a[5], vdd, w);
  tranif0 nmos_7(a[7], vdd, w);
  tranif0 nmos_8(a[9], vdd, w);
  tranif0 pmos_0(a[1], vdd, w);
endmodule   /* netlistTests__VerilogTest1LowB */

module VerilogTest1(w);
  input w;

  supply1 vdd;
  supply0 gnd;
  wire [9:0] net_5;

  netlistTests__VerilogTest1LowA d1_1(.a(net_5[9:0]), .w(w));
  netlistTests__VerilogTest1LowB d2_0(.w(w), .a({net_5[9], net_5[8], net_5[7], 
      net_5[6], net_5[5], net_5[4], net_5[3], net_5[2], net_5[1], net_5[0]}));
endmodule   /* VerilogTest1 */
